1. Technical Field
This disclosure relates to switching voltage regulators and more particularly to a control circuit with hysteresis adapted to drive a switching power stage of a switching voltage regulator, a relative switching voltage regulator and a method of controlling a switching voltage regulator.
2. Description of the Related Art
Voltage regulators generate a constant DC output voltage and contain circuits that keep the output voltage on a supplied load at a regulated value. This task is typically accomplished using a switching power stage, the switches of which are turned on/off depending on the logic state of a driving signal produced by a regulator control circuit.
A classic architecture of a feedback switching regulator controlled in constant-on-time (COT) mode is shown by way of example in FIG. 1. It comprises an error amplifier EA that generates an error signal VERR corresponding to the difference between a feedback signal FB, representing the regulated output voltage Vout, and a reference voltage Vref, a comparator COMP of the error signal VERR with a threshold Vth, adapted to generate an active flag S when the error signal crosses the threshold. At each active transition edge of the flag S, the monostable multivibrator MON generates a pulse command active for a pre-established time interval Ton that fixes the on-time of the power switches such to power the supplied load.
A more detailed architecture corresponding to that of FIG. 1 is shown in FIG. 2. The error signal VERR is tied to the output voltage VOUT by the following relation:
      V    ERR    =            V      OUT        ⁢                            R                      o            ⁢                                                  ⁢            2                                                R                          o              ⁢                                                          ⁢              1                                +                      R                          o              ⁢                                                          ⁢              2                                          ·              g        m            ·              (                              R            C                    +                      sC            INT                          )            and the comparison threshold Vth is given by the following equation:Vth=kRLIL 
This known architecture generates overshoots when the load decreases just after a constant on-time pulse is started. As schematically illustrated in the exemplary graph of FIG. 3, an overshoot of the output voltage VOUT occurs because the current requested by the load drops abruptly from about 13 A to about 8 A immediately after a new cycle is started.
In order to reduce this undesired effect, the architecture of FIG. 4 has been proposed in literature. Differently from the architecture of FIG. 1, it comprises a hysteresis comparator COMP with a hysteresis voltage Vhyst and a set-reset latch S/R for determining the on-time of the power stage switches. This solution reduces voltage overshoots because the hysteresis comparator shortens the on-time of the switches of the power stage in case of a reduction of the load.
A power supply controller similar to that of FIG. 4 is disclosed in the published patent application US 2008/0129264 and is shown in FIG. 5. The power-supply controller includes a voltage divider 32, an error amplifier 34, an analog-to-digital converter (ADC) 36, a signal combiner (here an adder) 38 for generating a control signal CONTROL, a low-pass filter 40, a signal generator 42, which generates the switching signal PWM and which includes a hysteresis comparator 44 and a reset-set (R/S) flip-flop 46, and a frequency adjuster 48 for generating a frequency-adjust signal. The error amplifier 34 and the analog-to-digital converter 36 generate an error voltage (Vout−Vref)/X corresponding to the difference between a reference voltage Vref and a feedback voltage representing the regulated output voltage Vout. A frequency adjuster 48 compares the switching frequency of the driving signal PWM, provided to the power stage of the regulator, with a reference frequency Freference and generates a corresponding frequency adjustment signal. An adder 38 combines these two signals and the combination of these two signals is transmitted, via a low-pass filter 40, to a hysteretic comparator 44, that sets or resets a S/R flip-flop 46 that generates the driving signal PWM. In practice, the known control circuit of FIG. 5 adjusts the hysteresis window with which the error voltage (Vout−Vref)/X is compared, in order to take into account transient frequencies of the load.